Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

4 comments

• brucehoult 7 months ago

  See the original 2018 post

  https://news.ycombinator.com/item?id=17852876

• Rochus 7 months ago

  > implemented in Verilog from scratch in one night

  Cool, but the "night" actually started in 2018 and lasted over seven years and 384 commits so far ;-)

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  • brucehoult 7 months ago

    See the original 2018 post

    https://news.ycombinator.com/item?id=17852876

  • snvzz 7 months ago

    It was working after just one night of work, is what they probably meant.

    Then they didn't discard it, but maintained it instead.