Note that this is very early work - one of the papers (the HUST one from this June) shows an 8x8 cell device, i.e. 64 bits in SLC mode.
DRAM kind of plateaued in 2011, when it hit $4/GB; since then it's gotten faster and bigger, but not appreciably cheaper per bit.
This could change if there was a way to do 3D DRAM, like 3D NAND flash, but that doesn't appear to be on the table at present. Note that this isn't the "stacking" they talk about with IGZO-DRAM, where they build layers on top of each other - it's not 3D stacking itself that made flash cheap.
Flash got insanely cheap because of the single-pass 3D architecture - it's pretty cheap to put a large number (~400 nowadays) of featureless layers onto a chip, then you drill precise holes through all the layers and coat the inside of the hole with the right stuff, turning each hole into a stack of ~400 flash cells.
The cost of a wafer (and thus a chip) is proportional to the time it spends in the ultra-expensive part of the fab. 3D NAND puts maybe 100x as many cells onto a wafer as the old planar flash (you can't pack those holes as closely as the old cells), but what's important is that the wafer only spends maybe 2x as long (I'm totally guessing here) in the fab. If it took 100x as long, laying down a few hundred layers, the price advantage would vanish.
3D ram stacking still would have significant benefits since the amount of board space taken up by RAM is significant. Quadrupling capacity per area would be a game-changer for GPUs with HBM, and could allow for a CAMM like standard to make it's way into servers.
They can do it with 3D NAND because the electrons are injected into the charge storage medium through brute force. The problem is that the capacitance scales with area. We're reducing the node size but now the aspect ratios are insane and the trenches for the storage wells are >3um high. That's over 1,000 times thicker per layer compared to NAND.
>> Through the years, imec has made considerable progress in assessing, understanding, and modeling reliability failure, paving the way to building reliable IGZO transistors with a target lifetime of five years
Five year lifetime isn't getting anywhere near my setup. Also notably absent was anything about read or write times. It sounded promising all the way up to that last paragraph.
The read and write times are apparently in the ~10ns range which is within the allowable range for DRAM (you'll have another 50-100 from the connectivity anyway)
It would be a waste to use this to just make DIMMs. It's only transistors, like SRAM cells, so you can efficiently fab them on the same process technology and the same dies as your logic.
Then again, there is wear, so either you accept a level of performance degeneration (dynamic capacity cache?) or you go to DIMMs anyway servicability.
It should be noted that the claim that the new DRAM cell has no capacitor can be misleading.
Like any DRAM cell, it has a capacitor, which in this case is the gate capacitor of a MOS transistor.
The separate capacitor of current DRAM cells is replaced by a second transistor, whose gate capacitor stores the charge that distinguishes stored "1"s from stored "0"s. Such 2-transistor cells, where the second transistor used for sensing the cell state also includes the capacitor, are not new, they had been used in many early DRAM devices, decades ago.
The main advantage of the new cell is in replacing silicon for the transistors of the DRAM cell with another semiconductor material with wider bandgap than silicon.
This reduces a lot the leakage currents, allowing a smaller capacitor. The gate capacitor of the storage transistor is sufficient, so no other separate capacitor is needed.
One thing that is not mentioned is how resistant are the new DRAM cells to radiation. The smaller stored charge makes them more susceptible, but the wider bandgap of the transistors makes them less susceptible, so it is uncertain which is the actual behavior.
Each cell has 2 transistors and a length of trace. Why not use the 2 transistors as a flip-flop? Then there is no charge decay.
Thinking in the same vein - transistors are really small now. Aren't we at the stage where we can drop DRAM and replace transistor+capacitor with 2 transistors as a flip-flop? It would save all that refresh time and controller circuitry.
You cannot make an RS latch with 2 transistors, much less a flip-flop, which is at least 50% more complex than a latch (a flip-flop differs from a latch because its state changes only on clock transitions; this is not needed for a memory, so memories use only the simpler latches).
You can make a latch with 2 transistors and 2 resistors, but resistors are more expensive than transistors in an integrated circuit, so the minimal latch has 4 transistors.
However with simple latches you cannot build a memory, because there must be a way to address them. Therefore you must add 2 pass transistors for cell addressing, thus you end with a 6-transistor SRAM cell. In the past there have been some SRAMs with so-called 4-transistor cells, but that is a misnomer, because those were 6-transistor cells where 2 transistors were passive, having their gates connected permanently to fixed potentials, making the transistors a substitute for resistors.
A 6-T SRAM cell has a few not-so-good characteristics, so for maximum performance, like in the first-level cache memory, more complex 8-transistor SRAM cells are used.
Even the simplest SRAM cell is much more complex than a DRAM cell, flash memory cell or ROM cell.
The ideal memory cell has the area of a square whose side is double the resolution of the available photolithography, because any cell must be at the intersection of a row and a column, where the row and the column must contain at least one conductor trace.
By 3-dimensional stacking of the memory cell components, some variants of DRAM cells, including the cell from TFA, may reach the ideal memory cell size.
> Through the years, imec has made considerable progress in assessing, understanding, and modeling reliability failure, paving the way to building reliable IGZO transistors with a target lifetime of five years
Replacing your DRAM sticks every five years may be okay, but what about for boards with soldered on memory?
If a Single Cell has a lifetime of 5 years (of hopefully constant r/w cycles) than with a few reserve cells and a controller like an ssd you could propably get decades of lifetime on a stick.
That isn't the impression I get. It's not a wear issue so much as a natural degregation of the materials. It's something that is being worked on for the technology to be viable.
You can't use a single cell of RAM at GHz frequencies. By the time you read a value and write another value back, you're talking about ~200ns so you are capped at ~5mhz writes (and anything that you are actually trying to access that quickly will be in caches anyway so your writes won't make it out to the DRAM unless you explicitly flush the caches)
Skimming through the linked paper, I can't actually find that claim being backed up anywhere?
The abstract does indeed say "It was found that the system reliability decreases to 0.84 after 1·10^8s at a stressing temperature of 300K", but I can't find anything close to that in the sections about Bias Temperature Instability or Hot Carrier Injection.
The only thing which to me looks close is the rather acute failure in the Radiation Trapping section - but that also states that the failure mode is dependent more on the total dose than time, and the total dose at which it fails is somewhere between 126 krad - 1.26 Mrad. For reference, a dose of 1 krad is universally fatal to a human.
In other words: don't put unshielded DRAM in a nuclear reactor?
I included the page number with the link, to prevent this, and also noted that these were modeled failures. I had trouble finding any real world data, which is where the google comment came in.
Yikes! Things that you don't necessarily want to know. Another one is that GPUs are released crawling with bugs - only the ones without cheap driver workarounds are fixed.
Yes, but most memory workloads don't store the same value for 15+ minutes at a time. And if you're using it as long-term storage (so basically a flash alternative) that 15-minute retention time is awfully low.
Note that this is very early work - one of the papers (the HUST one from this June) shows an 8x8 cell device, i.e. 64 bits in SLC mode.
DRAM kind of plateaued in 2011, when it hit $4/GB; since then it's gotten faster and bigger, but not appreciably cheaper per bit.
This could change if there was a way to do 3D DRAM, like 3D NAND flash, but that doesn't appear to be on the table at present. Note that this isn't the "stacking" they talk about with IGZO-DRAM, where they build layers on top of each other - it's not 3D stacking itself that made flash cheap.
Flash got insanely cheap because of the single-pass 3D architecture - it's pretty cheap to put a large number (~400 nowadays) of featureless layers onto a chip, then you drill precise holes through all the layers and coat the inside of the hole with the right stuff, turning each hole into a stack of ~400 flash cells.
The cost of a wafer (and thus a chip) is proportional to the time it spends in the ultra-expensive part of the fab. 3D NAND puts maybe 100x as many cells onto a wafer as the old planar flash (you can't pack those holes as closely as the old cells), but what's important is that the wafer only spends maybe 2x as long (I'm totally guessing here) in the fab. If it took 100x as long, laying down a few hundred layers, the price advantage would vanish.
3D ram stacking still would have significant benefits since the amount of board space taken up by RAM is significant. Quadrupling capacity per area would be a game-changer for GPUs with HBM, and could allow for a CAMM like standard to make it's way into servers.
They can do it with 3D NAND because the electrons are injected into the charge storage medium through brute force. The problem is that the capacitance scales with area. We're reducing the node size but now the aspect ratios are insane and the trenches for the storage wells are >3um high. That's over 1,000 times thicker per layer compared to NAND.
>> Through the years, imec has made considerable progress in assessing, understanding, and modeling reliability failure, paving the way to building reliable IGZO transistors with a target lifetime of five years
Five year lifetime isn't getting anywhere near my setup. Also notably absent was anything about read or write times. It sounded promising all the way up to that last paragraph.
The read and write times are apparently in the ~10ns range which is within the allowable range for DRAM (you'll have another 50-100 from the connectivity anyway)
It would be a waste to use this to just make DIMMs. It's only transistors, like SRAM cells, so you can efficiently fab them on the same process technology and the same dies as your logic.
Then again, there is wear, so either you accept a level of performance degeneration (dynamic capacity cache?) or you go to DIMMs anyway servicability.
https://www.imec-int.com/en/articles/capacitor-less-igzo-bas...
The graph on this page is awful, but those endurance lines on the right side are going up toward a century at optimal temperature.
I think we'll have to wait and see.
Agreed, but remember how bad flash memory was in the early SSD days.
I've watched a video about this DRAM tech, looklike the write cycle lifetime is acceptable for typical usecase
It should be noted that the claim that the new DRAM cell has no capacitor can be misleading.
Like any DRAM cell, it has a capacitor, which in this case is the gate capacitor of a MOS transistor.
The separate capacitor of current DRAM cells is replaced by a second transistor, whose gate capacitor stores the charge that distinguishes stored "1"s from stored "0"s. Such 2-transistor cells, where the second transistor used for sensing the cell state also includes the capacitor, are not new, they had been used in many early DRAM devices, decades ago.
The main advantage of the new cell is in replacing silicon for the transistors of the DRAM cell with another semiconductor material with wider bandgap than silicon.
This reduces a lot the leakage currents, allowing a smaller capacitor. The gate capacitor of the storage transistor is sufficient, so no other separate capacitor is needed.
One thing that is not mentioned is how resistant are the new DRAM cells to radiation. The smaller stored charge makes them more susceptible, but the wider bandgap of the transistors makes them less susceptible, so it is uncertain which is the actual behavior.
Video coverage of this story by Ian Cutress: https://youtu.be/ITdkH7PCu74
(you may need to adjust the volume, the audio is 5 LU below reference)
Oh hey, that's Dr. Ian Cuttress - I loved reading his pieces on anandtech. I wondered what he'd been up to, thanks for sharing!
Some people are even considering this as a possibly viable path to compute on memory.
For example: https://www.science.org/doi/10.1126/sciadv.adu4323
I have been banging on about DRAM doesn't scale for a long time. And this is the first time we have something that fundamentally changes DRAM.
We could have higher capacity, faster and most importantly far more energy efficient DRAM.
Each cell has 2 transistors and a length of trace. Why not use the 2 transistors as a flip-flop? Then there is no charge decay.
Thinking in the same vein - transistors are really small now. Aren't we at the stage where we can drop DRAM and replace transistor+capacitor with 2 transistors as a flip-flop? It would save all that refresh time and controller circuitry.
You cannot make an RS latch with 2 transistors, much less a flip-flop, which is at least 50% more complex than a latch (a flip-flop differs from a latch because its state changes only on clock transitions; this is not needed for a memory, so memories use only the simpler latches).
You can make a latch with 2 transistors and 2 resistors, but resistors are more expensive than transistors in an integrated circuit, so the minimal latch has 4 transistors.
However with simple latches you cannot build a memory, because there must be a way to address them. Therefore you must add 2 pass transistors for cell addressing, thus you end with a 6-transistor SRAM cell. In the past there have been some SRAMs with so-called 4-transistor cells, but that is a misnomer, because those were 6-transistor cells where 2 transistors were passive, having their gates connected permanently to fixed potentials, making the transistors a substitute for resistors.
A 6-T SRAM cell has a few not-so-good characteristics, so for maximum performance, like in the first-level cache memory, more complex 8-transistor SRAM cells are used.
Even the simplest SRAM cell is much more complex than a DRAM cell, flash memory cell or ROM cell.
The ideal memory cell has the area of a square whose side is double the resolution of the available photolithography, because any cell must be at the intersection of a row and a column, where the row and the column must contain at least one conductor trace.
By 3-dimensional stacking of the memory cell components, some variants of DRAM cells, including the cell from TFA, may reach the ideal memory cell size.
Traditional CMOS D-flipflop takes 16 transistors, SRAM cell takes 6 (two looped inverters and two data-line selection transistors).
The capacitor in DRAM is usually realised as an enlarged gate of a transistor AFAIK.
> Through the years, imec has made considerable progress in assessing, understanding, and modeling reliability failure, paving the way to building reliable IGZO transistors with a target lifetime of five years
Replacing your DRAM sticks every five years may be okay, but what about for boards with soldered on memory?
If a Single Cell has a lifetime of 5 years (of hopefully constant r/w cycles) than with a few reserve cells and a controller like an ssd you could propably get decades of lifetime on a stick.
That isn't the impression I get. It's not a wear issue so much as a natural degregation of the materials. It's something that is being worked on for the technology to be viable.
Their graphs show it as being voltage-dependent, so there's definitely some wear component involved.
> paving the way to building reliable IGZO transistors with a target lifetime of five years
It almost makes it seem like they want their memory to last five years, as though it's a feature.
10^11 cycles is not “practically unlimited endurance”, that’s less than a second of use at 1 GHz
You can't use a single cell of RAM at GHz frequencies. By the time you read a value and write another value back, you're talking about ~200ns so you are capped at ~5mhz writes (and anything that you are actually trying to access that quickly will be in caches anyway so your writes won't make it out to the DRAM unless you explicitly flush the caches)
200ns seems a bit high. But, if you do the math, you'll find that's a practically negligible difference, at only 6 hours at 5MHz.
DRAM appears to be closer to 300 hours, at reasonable temperatures [1], at the worst case workload.
It would be interesting if Google released their failure rates, like they did with hard disk vs ssd.
[1] modeled failures, page 75: https://repository.tudelft.nl/record/uuid:e36c2de7-a8d3-4dfa...
Skimming through the linked paper, I can't actually find that claim being backed up anywhere?
The abstract does indeed say "It was found that the system reliability decreases to 0.84 after 1·10^8s at a stressing temperature of 300K", but I can't find anything close to that in the sections about Bias Temperature Instability or Hot Carrier Injection.
The only thing which to me looks close is the rather acute failure in the Radiation Trapping section - but that also states that the failure mode is dependent more on the total dose than time, and the total dose at which it fails is somewhere between 126 krad - 1.26 Mrad. For reference, a dose of 1 krad is universally fatal to a human.
In other words: don't put unshielded DRAM in a nuclear reactor?
I included the page number with the link, to prevent this, and also noted that these were modeled failures. I had trouble finding any real world data, which is where the google comment came in.
>DRAM appears to be closer to 300 hours
Yikes! Things that you don't necessarily want to know. Another one is that GPUs are released crawling with bugs - only the ones without cheap driver workarounds are fixed.
Sure, but conventional DRAM endurance is 10^15 or more
> >10^3s retention, >10^11 cycles endurance
The implication is that it can theoretically hold a value for 10^14s (~3 million years).
Yes, but most memory workloads don't store the same value for 15+ minutes at a time. And if you're using it as long-term storage (so basically a flash alternative) that 15-minute retention time is awfully low.
Decades of research into optimizing DRAM refresh efficiency suggests that you don’t understand how the world is using DRAM.