Pretty epic. A very impressive case of building one's own tools, or, rather, a one-off tool that seems to do a simple thing. The most impressive aspect is, of course, handling various issues that normally would require making a new PCB, but the author never retreated.
> Unfortunately, having all of the transceivers in a single quad was a bit limiting due to the 7 series clocking architecture: they share the same QPLL, which has to be at 10.3125 Gbps for 10Gbase-R operation. While the CPLLs can be configured freely, they have a lower Fmax which meant that the BERT / CDR trigger channels cannot operate at arbitrary frequencies above 6 Gbps (most notably, 8 Gbps operation for PCIe gen3 mode is not available).
This one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.
Yeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.
> My original plan had been to use their standard 1U folded sheet metal design, but I discovered too late, after boards were ordered, that it wasn’t going to work due to the 5mm corner mounting holes being inside the keepout area for the rear bend.
I wonder if a less annoying solution would have been to omit the mounting holes and then drill and tap them after the fact, possibly at a slight angle if the metal is out of plane there.
Soldered an ESP32 together with a couple I2C sensors the other week. Didn’t work. Read post, jaw hit floor, maybe I’ll revisit the project soon. Amazing.
This is a really beautiful bit of kit, really like the case and the thought given to signing, but the analog side is really impressive too. Would it be viable to use the same hardware as a base for an NTP server?
Pretty epic. A very impressive case of building one's own tools, or, rather, a one-off tool that seems to do a simple thing. The most impressive aspect is, of course, handling various issues that normally would require making a new PCB, but the author never retreated.
I imagine he'll post the files, so they won't be a one-off.
They’re already linked from the article - https://github.com/azonenberg/triggercrossbar/
Yep. Although given all of the bugs, I don't recommend anyone try to build one without forking and making substantial design changes :)
Thanks! I had missed that!
The "root canal" side quest was definitely something. Kudos to author
> Unfortunately, having all of the transceivers in a single quad was a bit limiting due to the 7 series clocking architecture: they share the same QPLL, which has to be at 10.3125 Gbps for 10Gbase-R operation. While the CPLLs can be configured freely, they have a lower Fmax which meant that the BERT / CDR trigger channels cannot operate at arbitrary frequencies above 6 Gbps (most notably, 8 Gbps operation for PCIe gen3 mode is not available).
I'm glad someone understands this.
This one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.
Yeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.
> My original plan had been to use their standard 1U folded sheet metal design, but I discovered too late, after boards were ordered, that it wasn’t going to work due to the 5mm corner mounting holes being inside the keepout area for the rear bend.
I wonder if a less annoying solution would have been to omit the mounting holes and then drill and tap them after the fact, possibly at a slight angle if the metal is out of plane there.
The author is Andrew Zonenberg. For those unfamiliar, this qualifies as a "medium complexity" (!) project for him. His stuff is always a great read.
Soldered an ESP32 together with a couple I2C sensors the other week. Didn’t work. Read post, jaw hit floor, maybe I’ll revisit the project soon. Amazing.
Amazing levels of depth and detail here. I wonder what sort of choices I need to make to eventually acquire a lab like this.
This is super impressive. Additionally, I had never heard about ngscopeclient before. Amazingly cool software!
This is a really beautiful bit of kit, really like the case and the thought given to signing, but the analog side is really impressive too. Would it be viable to use the same hardware as a base for an NTP server?
You could build an NTP server with much less horsepower (and of course without all of the high speed I/O etc).
The ones from Leo Bodnar are decent.
This is very impressive.